Table of Contents

Preface     xix
Acknowledgments     xxvii
About the Authors     xxix
Chapter 1  Engineering the Power Delivery Network     1
1.1  What Is the Power Delivery Network (PDN) and Why Should I Care?     1
1.2  Engineering the PDN     5
1.3  “Working” or “Robust” PDN Design     8
1.4  Sculpting the PDN Impedance Profile     12
1.5  The Bottom Line     14
Reference     15
Chapter 2  Essential Principles of Impedance for PDN Design     17
2.1  Why Do We Care About Impedance?     17
2.2  Impedance in the Frequency Domain     18
2.3  Calculating or Simulating Impedance     21
2.4  Real Circuit Components vs Ideal Circuit Elements     26
2.5  The Series RLC Circuit     30
2.6  The Parallel RLC Circuit     34
2.7  The Resonant Properties of a Series and Parallel RLC Circuit     36
2.8  Examples of RLC Circuits and Real Capacitors     42
2.9  The PDN as Viewed by the Chip or by the Board     46
2.10  Transient Response     52
2.11  Advanced Topic: The Impedance Matrix     56
2.12  The Bottom Line     66
References     68
Chapter 3  Measuring Low Impedance     69
3.1  Why Do We Care About Measuring Low Impedance?     69
3.2  Measurements Based on the V/I Definition of Impedance     70
3.3  Measuring Impedance Based on the Reflection of Signals     71
3.4  Measuring Impedance with a VNA     76
3.5  Example: Measuring the Impedance of Two Leads in a DIP     81
3.6  Example: Measuring the Impedance of a Small Wire Loop     86
3.7  Limitations of VNA Impedance Measurements at Low Frequency     89
3.8  The Four-Point Kelvin Resistance Measurement Technique     93
3.9  The Two-Port Low Impedance Measurement Technique     95
3.10  Example: Measuring the Impedance of a 1-inch Diameter Copper Loop     102
3.11  Accounting for Fixture Artifacts     105
3.12  Example: Measured Inductance of a Via     109
3.13  Example: Small MLCC Capacitor on a Board     114
3.14  Advanced Topic: Measuring On-Die Capacitance     120
3.15  The Bottom Line     134
References     136
Chapter 4  Inductance and PDN Design     137
4.1  Why Do We Care About Inductance in PDN Design?     137
4.2  A Brief Review of Capacitance to Put Inductance in Perspective     138
4.3  What Is Inductance? Essential Principles of Magnetic Fields and Inductance     141
4.4  Impedance of an Inductor     147
4.5  The Quasi-Static Approximation for Inductance     150
4.6  Magnetic Field Density, B     155
4.7  Inductance and Energy in the Magnetic Field     159
4.8  Maxwell’s Equations and Loop Inductance     163
4.9  Internal and External Inductance and Skin Depth     167
4.10  Loop and Partial, Self- and Mutual Inductance     172
4.11  Uniform Round Conductors     175
4.12  Approximations for the Loop Inductance of Round Loops     179
4.13  Loop Inductance of Wide Conductors Close Together     182
4.14  Approximations for the Loop Inductance of Any Uniform Transmission Line     188
4.15  A Simple Rule of Thumb for Loop Inductance     194
4.16  Advanced Topic: Extracting Loop Inductance from the S-parameters Calculated with a 3D Field Solver     195
4.17  The Bottom Line     202
References     204
Chapter 5  Practical Multi-Layer Ceramic Chip Capacitor Integration     205
5.1  Why Use Capacitors?     205
5.2  Equivalent Circuit Models for Real Capacitors     206
5.3  Combining Multiple Identical Capacitors in Parallel     209
5.4  The Parallel Resonance Frequency Between Two Different Capacitors     211
5.5  The Peak Impedance at the PRF     215
5.6  Engineering the Capacitance of a Capacitor     220
5.7  Capacitor Temperature and Voltage Stability     222
5.8  How Much Capacitance Is Enough?     225
5.9  The ESR of Real Capacitors: First- and Second-Order Models     229
5.10  Estimating the ESR of Capacitors from Spec Sheets     234
5.11  Controlled ESR Capacitors     238
5.12  Mounting Inductance of a Capacitor     240
5.13  Using Vendor-Supplied S-parameter Capacitor Models     251
5.14  How to Analyze Vendor-Supplied S-Parameter Models     254
5.15  Advanced Topics: A Higher Bandwidth Capacitor Model     258
5.16  The Bottom Line     272
References     274
Chapter 6  Properties of Planes and Capacitors     275
6.1  The Key Role of Planes     275
6.2  Low-Frequency Property of Planes: Parallel Plate Capacitance     278
6.3  Low-Frequency Property of Planes: Fringe Field Capacitance     279
6.4  Low-Frequency Property of Planes: Fringe Field Capacitance in Power Puddles     285
6.5  Loop Inductance of Long, Narrow Cavities     290
6.6  Spreading Inductance in Wide Cavities     292
6.7  Extracting Spreading Inductance from a 3D Field Solver     304
6.8  Lumped-Circuit Series and Parallel Self-Resonant Frequency     307
6.9  Exploring the Features of the Series LC Resonance     312
6.10  Spreading Inductance and Source Contact Location     315
6.11  Spreading Inductance Between Two Contact Points     317
6.12  The Interactions of a Capacitor and Cavities     325
6.13  The Role of Spreading Inductance: When Does Capacitor Location Matter?     327
6.14  Saturating the Spreading Inductance     332
6.15  Cavity Modal Resonances and Transmission Line Properties     334
6.16  Input Impedance of a Transmission Line and Modal Resonances     340
6.17  Modal Resonances and Attenuation     343
6.18  Cavity Modes in Two Dimensions     347
6.19  Advanced Topic: Using Transfer Impedance to Probe Spreading Inductance     354
6.20  The Bottom Line     361
References     362
Chapter 7  Taming Signal Integrity Problems When Signals Change Return Planes     363
7.1  Signal Integrity and Planes     363
7.2  Why the Peak Impedances Matter     364
7.3  Reducing Cavity Noise through Lower Impedance and Higher Damping     367
7.4  Suppressing Cavity Resonances with Shorting Vias     372
7.5  Suppressing Cavity Resonances with Many DC Blocking Capacitors     383
7.6  Estimating the Number of DC Blocking Capacitors to Suppress Cavity Resonances     387
7.7  Determining How Many DC Blocking Capacitors Are Needed to Carry Return Current     393
7.8  Cavity Impedance with a Suboptimal Number of DC Blocking Capacitors     397
7.9  Spreading Inductance and Capacitor Mounting Inductance     401
7.10  Using Damping to Suppress Parallel Resonant Peaks Created by a Few Capacitors     403
7.11  Cavity Losses and Impedance Peak Reduction     408
7.12  Using Multiple Capacitor Values to Suppress Impedance Peak     411
7.13  Using Controlled ESR Capacitors to Reduce Peak Impedance Heights     414
7.14  Summary of the Most Important Design Principles for Managing Return Planes     418
7.15  Advanced Topic: Modeling Planes with Transmission Line Circuits     419
7.16  The Bottom Line     423
References     425
Chapter 8  The PDN Ecology     427
8.1  Putting the Elements Together: The PDN Ecology and the Frequency Domain     428
8.2  At the High-Frequency End: The On-Die Decoupling Capacitance     430
8.3  The Package PDN     440
8.4  The Bandini Mountain     447
8.5  Estimating the Typical Bandini Mountain Frequency     452
8.6  Intrinsic Damping of the Bandini Mountain     456
8.7  The Power Ground Planes with Multiple Via Pair Contacts     460
8.8  Looking from the Chip Through the Package into the PCB Cavity     465
8.9  Role of the Cavity: Small Boards, Large Boards, and “Power Puddles”     469
8.10  At the Low Frequency: The VRM and Its Bulk Capacitor     476
8.11  Bulk Capacitors: How Much Capacitance Is Enough?     479
8.12  Optimizing the Bulk Capacitor and VRM     483
8.13  Building the PDN Ecosystem: The VRM, Bulk Capacitor, Cavity, Package, and On-Die Capacitance     488
8.14  The Fundamental Limits to the Peak Impedance     492
8.15  Using One Value MLCC Capacitor on the Board-General Features     498
8.16  Optimizing the Single MLCC Capacitance Value     502
8.17  Using Three Different Values of MLCC Capacitors on the Board     507
8.18  Optimizing the Values of Three Capacitors     511
8.19  The Frequency Domain Target Impedance Method (FDTIM) for Selecting Capacitor Values and the Minimum Number of Capacitors     514
8.20  Selecting Capacitor Values with the FDTIM     516
8.21  When the On-Die Capacitance Is Large and Package Lead Inductance Is Small     521
8.22  An Alternative Decoupling Strategy Using Controlled ESR Capacitors     527
8.23  On-Package Decoupling (OPD) Capacitors     532
8.24  Advanced Section: Impact of Multiple Chips on the Board Sharing the Same Rail     540
8.25  The Bottom Line     543
References     545
Chapter 9  Transient Currents and PDN Voltage Noise     547
9.1  What’s So Important About the Transient Current?     547
9.2  A Flat Impedance Profile, a Transient Current, and a Target Impedance     550
9.3  Estimating the Transient Current to Calculate the Target Impedance with a Flat Impedance Profile     552
9.4  The Actual PDN Current Profile Through a Die     553
9.5  Clock-Edge Current When Capacitance Is Referenced to Both Vss and Vdd     558
9.6  Measurement Example: Embedded Controller Processor     562
9.7  The Real Origin of PDN Noise—How Clock-Edge Current Drives PDN Noise     565
9.8  Equations That Govern a PDN Impedance Peak     572
9.9  The Most Important Current Waveforms That Characterize the PDN     577
9.10  PDN Response to an Impulse of Dynamic Current     579
9.11  PDN Response to a Step Change in Dynamic Current     582
9.12  PDN Response to a Square Wave of Dynamic Current at Resonance     585
9.13  Target Impedance and the Transient and AC Steady-State Responses     589
9.14  Impact of Reactive Elements, q-Factor, and Peak Impedances on PDN Voltage Noise     595
9.15  Rogue Waves     602
9.16  A Robust Design Strategy in the Presence of Rogue Waves     610
9.17  Clock-Edge Current Impulses from Switched Capacitor Loads     613
9.18  Transient Current Waveforms Composed of a Series of Clock Impulses     622
9.19  Advanced Section: Applying Clock Gating, Clock Swallowing, and Power Gating to Real CMOS Situations     629
9.20  Advanced Section: Power Gating     633
9.21  The Bottom Line     638
References     640
Chapter 10  Putting It All Together: A Practical Approach to PDN Design     643
10.1  Reiterating Our Goal in PDN Design     643
10.2  Summary of the Most Important Power Integrity Principles     645
10.3  Introducing a Spreadsheet to Explore Design Space     654
10.4  Lines 1-12: PDN Input Voltage, Current, and Target Impedance Parameters     658
10.5  Lines 13-24: 0th Dip (Clock-Edge) Noise and On-Die Parameters     661
10.6  Extracting the Mounting Inductance and Resistance     665
10.7  Analyzing Typical Board and Package Geometries for Inductance     674
10.8  The Three Loops of the PDN Resonance Calculator (PRC) Spreadsheet     677
10.9  The Performance Figures of Merit     682
10.10  Significance of Damping and q-factors     685
10.11  Using a Switched Capacitor Load Model to Stimulate the PDN     694
10.12  Impulse, Step, and Resonance Response for Three-Peak PDN: Correlation to Transient Simulation     696
10.13  Individual q-factors in Both the Frequency and Time Domains     703
10.14  Rise Time and Stimulation of Impedance Peak     710
10.15  Improvements for a Three-Peak PDN: Reduced Loop Inductance of the Bandini Mountain and Selective MLCC Capacitor Values     718
10.16  Improvements for a Three-Peak PDN: A Better SMPS Model     722
10.17  Improvements for a Three-Peak PDN: On-Package Decoupling (OPD) Capacitors     724
10.18  Transient Response of the PDN: Before and After Improvement     731
10.19  Re-examining Transient Current Assumptions     736
10.20  Practical Limitations: Risk, Performance, and Cost Tradeoffs     739
10.21  Reverse Engineering the PDN Features from Measurements     740
10.22  Simulation-to-Measurement Correlation     747
10.23  Summary of the Simulated and Measured PDN Impedance and Voltage Features     754
10.24  The Bottom Line     757
References     759
Index     761